Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of integrated circuits or semiconductor devices on a single semiconductor product. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM), which uses a charge to store information.
Semiconductor devices are fabricated by sequentially depositing, patterning, and doping many insulating, conductive and semiconductor layers. Portions of integrated circuits are often connected to subsequently formed upper layers by forming holes over the circuits and then filling the holes with semiconductor or conductive material to form vias or contacts. The term “contact” used herein refers also to vias.
One method of making contact to an underlying electronic circuit or component region is by forming borderless contacts, as shown in FIGS. 1 and 2. FIG. 1 illustrates a perspective view of a wordline and bitline wiring structure disposed over a memory array such as a DRAM device 100. FIG. 2 shows a cross-sectional view of the DRAM device 100 shown in FIG. 1. Component regions 102 which may comprise DRAM memory cells are formed in a workpiece 120. Wordlines 104 are positioned perpendicular to bitlines 1112, with each intersection of a wordline 104 and bitline 112 being proximate a DRAM memory cell or component region 102 so that the cell can be accessed (e.g., read from or written to). A nitride cap layer 106 is disposed over the top of each wordline 104, and nitride sidewall spacers 108 are formed over the sidewalls of the wordlines 104 and the nitride cap layer 106, as shown. The nitride cap layer 106 and sidewall spacers 108 provide electrical isolation for the wordlines 104 from subsequently formed bitlines 112 and borderless contacts 114.
An insulating material (not shown) is disposed between adjacent bitlines 112 and contacts 114. The insulating material is deposited, and the insulating material is patterned with the bitline 112 and contact 114 pattern. The bitlines 112 and contacts 114 are formed simultaneously in a damascene process as the insulating material is filled with a conductive material. The shape of the contacts 114 is defined by the sidewall spacers 108; thus, the contacts 114 are self-aligned with the underlying component regions 102 which may comprise a source or drain of an access transistor for a DRAM cell, for example. This self-aligning method of making contact to component regions 102 is referred to as a borderless contact 114 technique. Borderless contacts 114 are used often in the manufacturing of memory devices and other semiconductor device applications.
A problem with prior art borderless contact 114 formation methods and structures is that the nitride cap layer 106 can be eroded during the various etch processes, such as a reactive ion etch (RIE) which is often used to manufacture the device. If an excessive amount of the nitride cap layer 106 is eroded away, then shorts can be created between the wordlines 104 and bitlines 112, causing device failures and decreasing yields. For example, the insulating material the bitlines 112 and contacts 114 are formed in typically comprises an oxide. An etch selective to nitride is used to etch the oxide to form the bitline 112 and contact 114 pattern. However, this selective etch process may also etch away a portion or all of the nitride cap layer 106. As semiconductor devices are made smaller, reduced bitline capacitance is required, resulting in thinner insulating layers, further contributing to the nitride cap layer 106 erosion problem.
Thus, what is needed in the art is a method of manufacturing borderless contacts that preserves the nitride cap layer 106.